Descrição
About the opportunity:
The Hard IP Development Group (HIPD) within Intel's Central Engineering Organization develops leadership IPs for Server, Client, and Networking SOCs, as well as Intel Foundry Customers. The Electrical Validation and Debug group within HIPD directly engages with IP design teams and SOC customers in IP validation and debug for test chips and products.
This role focuses on mixed signal high-speed PHY post-silicon validation and debug, spanning IP enabling, customer sighting resolution, and cross-functional collaboration with SOC teams.
Key responsibilities:
• Generate test plans and test content for mixed signal high-speed PHY post-silicon validation, including characterization of Clocking, Transmitter, and Receiver blocks.
• Perform IO protocol debug across one or more of the following: PCIe, UCIe, DDR, or Ethernet, from both PHY recipe and firmware perspectives.
• Conduct SOC board design reviews, provide recommendations, and support post-silicon debug activities.
• Represent the IP team during SOC Power-Ons for test chips and products, providing hands-on IP enabling support through proper recipes and firmware versions for PCIe, UCIe, and USB PHYs.
• Identify clocking and PHY-related silicon issues, investigate, debug, and disposition customer bugs and sightings in a timely manner.
• Reproduce customer issues and drive root cause analysis through failure analysis and structured debug methodologies.
Qualifications:
• BS with 6+ years, MS with 4+ years, or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field.
• Relevant experience in electrical or bench post-silicon validation with one or more high-speed PHYs such as PCIe, USB, UCIe, DDR, Ethernet, or equivalent interface experience.
• Experience with lab hardware and software including Oscilloscopes, Logic Analyzers, Protocol Analyzers, and BERTs.
• Knowledge of one or more industry-standard IO specifications such as PCIe, USB, or Die-to-Die UCIe.
• Customer obsession with a strong sense of urgency in resolving technical issues.
• Versatility and adaptability when engaging across multiple teams, IPs, and debug scenarios.
• Collaborative mindset with the ability to work effectively with both IP design teams and SOC customers.
Nice to have:
• Experience with mixed signal IP characterization including PLLs, TX and RX jitter characterization.
• Experience leading IP debug efforts as situations arise, in addition to hands-on debug execution.
• Signal integrity and power delivery knowledge.
• Pre-silicon design or simulation experience in logic, circuits, firmware, MRC, or mixed signal validation.
Benefits:
• Competitive pay and stock bonuses.
• Comprehensive benefit programs including health, retirement, and vacation.
Job details:
• Job Type: Experienced Hire
• Shift: Shift 1 (United States of America)
• Primary Location: US, California, Folsom
• Additional Locations: US, California, Santa Clara
• Annual Salary Range: $141,910.00-200,340.00 USD
• Work Model: Hybrid work model allowing employees to split time between working on-site and off-site.
About the company:
Intel Corporation is a global technology leader, driving the future of compute and semiconductor innovation. The Central Engineering Organization designs powerful silicon products that power servers, clients, networking systems, and foundry customers worldwide.
Additional information:
Intel is committed to Responsible Business Alliance compliance and ethical hiring practices. No fees are charged during the hiring process.
Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.